Defect tolerant, fine-grained parallel testing of a Cell Matrix
Lisa J.K. Durbeck and Nicholas J. Macias
from Proceedings of SPIE ITCom 2002 Series, Vol. 4867 Copyright© 2002 SPIE
(Conference: Reconfigurable Technology: FPGAs and Recofigurable Processors for Computing and Communications IV (IT203), a subconference of ITCom, Boston, Massachusetts, USA, 29 July - 1 August 2002.)
This conference was sponsored by SPIE, the International Society for Optical Engineering
A fault testing methodology for a cell-based self configurable hardware platform (the Cell Matrix™) is described. Background on the Cell Matrix is given, including its amenability to use despite the presence of manufacturing defects. The ability of cells within the Cell Matrix to isolate faulty regions is also described. A method for testing individual cells, based on an external test driver, is discussed. The benefits of locating this test driver inside the device under test are explained. A method is described for efficient, autonomous, robust creation of a network of self-testing structures (called Supercells) for parallel implementation and execution of this test driver. Sample tests are described, and their results are given, demonstrating the effectiveness and robustness of the testing methodology. A discussion of the research, including conclusions, is presented. Plans for future work are discussed.
Keywords: Fault testing, reconfigurable hardware, self configurable, process driver, nanotechnology, autonomous, fault tolerance, Cell Matrix