Researcher Lukáš Sekanina finds biology-inspired computer hardware to be an interesting research area and a likely ingredient of the future. One biology-inspired research area that interests Sekanina is evolvable hardware and evolutionary algorithms. These are techniques for developing circuits or software by starting off with something, then improving it via operations modelled after Darwin's theory of evolution. An example is iterative circuit construction via selective transmittal of information from one iteration, or generation, to the next.
Sekanina is currently developing what he calls evolvable components, a project that is intended to permit someone writing a computer program in a high level language such as C++ to specify that certain sections of the code, or code "components," are to be evolved. His idea is to simplify the incorporation of genetic algorithms and evolvable hardware into new or existing software and applications by providing software and hardware support and a single, standard interface. Inside the programming language, the user provides the parameters for the evolution, such as the fitness function, using a standard template.
The evolution itself occurs in hardware, on off-the-shelf chips using a system designed by Sekanina. Hardware-level evolution, or intrinsic evolution, is expected to be preferable to software-based evolution because of the speedup involved in doing the computations and iterations directly in hardware. "Various chips will be needed for various classes of applications," says Sekanina. Accordingly, Sekanina's hardware-level evolution will include the capability to use three separate hardware targets, CPU/memory-based hardware, an FPGA, and a Cell Matrix. Evolution on a Cell Matrix is easy to conceive, says Sekanina, "because the object of evolution is clear: the truth tables of a set of cells."
Evolvable components can be used to replace one subsection of a program or a specific hardware circuit. The larger application will train the evolvable component to perform a specific function, and the application itself represents the (dynamic) environment in which the evolvable component resides and evolves. Sekanina predicts that, if he and others are successful, a circuit designer will oneday be able to go to a store such as Radio Shack and buy a piece of hardware that is an evolvable component specific to a class of problems and/or circuits, drop it into an application, and train it to behave like the desired circuit. Systems may eventually be made of components (code or circuits) written specifically for the system, combined with these evolvable components that have been evolved and adapted to work as parts of the system.
Sekanina is a Ph.D. candidate and teacher in the department of Faculty of Information Technology at Brno University of Technology in Brno, Czech Republic. He is currently in Norway working on a research project with Jim Třrresen from the Department of Informatics at the University of Oslo (site in English, site in Norwegian). There they are working on using evolvable hardware for a real-world application, a recognition system for traffic signs. One aspect of this work will be the automatic filtering of noisy image inputs using evolvable hardware.
Sekanina's research has spanned and integrated formal methods, efficiency testing, evolvable hardware, evolutionary algorithms, embedded hardware, software system design, and programming, and his thesis goal is to provide a "theoretical and formal approach to evolvable systems." Evolvable components are the subject of Sekanina's doctoral disseration. He is posting parts as he writes them, and so some ideas and several chapters can be viewed online already at his home pages.
Sekanina praised the Cell Matrix computing architecture as "a very simple idea, everybody can understand it, but very powerful and big impact." His interest in the architecture began with a journal article written by Prof. Dr. Hugo de Garis that reviewed the Evolvable Hardware Conference in 1999. In that article Sekanina learned of an intrinsic, parallel genetic algorithm by Nick Macias (called the Ringed G.A.), which Macias designed to take advantage of local, parallel interactions on Cell Matrix hardware (Macias 1999). Sekanina decided to test the degree of parallelism in the Ringed G.A.. In 2001, he presented a paper at the European Simulation Multiconference for which he used the Transim simulation tool, a tool for performance prediction of parallel architectures, to test the G.A.'s efficiency. Commenting on how easy it can be to do a first cut simulation of something when you have the right tools to do it, Sekanina showed a two page Transim program that he had written which allowed him to measure the efficiency of communications in Macias' Ringed G.A.. Sekanina's tests provided further validation of the performance numbers Macias stated in his EH 1999 paper: his results showed no decrease in efficiency as the number of processors is increased. "The time complexity is constant," says Sekanina.
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