The cells within a Cell Matrix™ are programmable, gate-level processors where a small set of properties holds true for cell structure, function, and intercellular communication. This set of cellular properties provides ways to directly program cells to bring about useful computations and data processing.
Cells are connected to their nearest neighbors and exchange data and configuration information with their neighbors. Individual cells perform logic gate-level functions on their inputs and send outputs to their n sides (n = 3, 4, 6, 8, etc; 4 outputs for a 4-sided cell). The functions a cell performs are dictated by a memory that holds the truth table or lookup table corresponding to the n desired functions. This truth table defines all outputs for all input combinations. Data a cell receives can be modified and passed onward, and can be modified in different ways to suit different neighbors.
Another slightly different way to think of a cell is as a junction point where a number of wires can be connected to each other, and not only can they be variably connected to each other, and to more than one wire, but a simple logic function (such as an AND or an OR) can be performed on the data before it is passed onward. The junction point where 6 inputs can be connected to produce up to 6 outputs is shown in this illustration. The relationship between inputs and outputs is programmed and fully specified by whatever you store in the cell's truth table, shown in this illustration as the center blue region. The additional set of lines on each edge of the hexagon is the C-mode input/output lines, described next.
Any neighboring cell can change the configuration of this cell by passing it a new truth table, which the neighbor does by sending this cell a signal to cause it to go into configuration mode (C-MODE) and then writing the truth table memory. Note that the data stream a cell receives from its neighbor could be either code or data, and the cell uses this second C-MODE signal to treat the incoming data stream as it was intended. It is also worth noting at this point that this is the underlying mechanism for implementing distributed configuration and control systems for any application of Cell Matrices.
Cells can be represented by a simple circuit. The largest component of a cell is the memory that holds the truth table, or lookup table. The remainder is wires and logic needed to write the truth table and to process and output data in D-MODE. The schematic diagram for a cell is presented in patent #6,297,667 for a shift-register type memory and in patent #6,222,381 for a nonshifting memory (access patents).
A Cell Matrix is simply a set of 2 or more cells, with their input/output lines connected to each other. Various two dimensional and three dimensional tilings of cells are possible, with different numbers of sides.
Our work to date has made it possible to translate algorithms, dataflow diagrams, and circuits to this Cell Matrix structure/function through straightforward application of standard electrical engineering practices. As the technology matures, it will be possible to program Cell Matrices using high level software languages as well.

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